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Geo-Spatial Outlier Detection

comparing die test consequences with other die on a wafer helps identify outliers, but combining that data with the accurate location of an outlier offers a tons deeper realizing of what can go incorrect and why.

The leading thought in outlier detection is to locate some thing in or on a die that is distinctive from all the different dies on a wafer. Doing this within the context of a die’s neighbor has develop into more convenient with state-of-the-paintings yield and check management records analytic structures, nonetheless it nevertheless can get advanced. Even the definition of a neighbor can vary.

Wafer spatial version has been used for some time to establish and decipher yield issues, however basically for put up-mortems of screw ups within the field. Product and first-class engineers increasingly are making use of this flow/fail verify selections, above all in safety-crucial or mission-vital functions, as a result of primary outlier detection techniques in line with half normal trying out (PAT) lack localization to without difficulty balance the yield/exceptional/can charge triangle.

thoughts beyond PAT count on dissimilar measurements, arithmetic operations on check effects to center of attention the circulate/fail big difference, and geo-spatial relationships. but geographical vicinity and linked verify results additionally require additional engineering elements, so at advanced nodes and in purposes where high-quality and reliability are simple, fees are going up.

“each and every time you make an incredible shift in know-how — such as aluminum-to-copper interconnects, and standard to high-ok steel gates — you have a brand new set of issues crop up that you haven’t seen before,” observed Ken Butler, strategic enterprise advent manager at Advantest america. “With every essential expertise shift and the smaller geometries, it became more and more necessary to stream faraway from basic information because they simply didn’t reduce it anymore.”

motivated by way of making a choice on downstream disasters, product engineers have looked to outlier-primarily based detection suggestions at wafer look at various to reveal burn-in disasters. And when constructing displays for look at various escapes, they naturally have turned to these outlier detection ideas. this is average apply for car chipmakers, which continuously practice outlier verify thoughts, and that they regularly have pioneered new methods. Now, different trade sectors are following with a more proactive method to outlier detection recommendations.

“whereas outlier detection could be an exceptional response to containing a test break out, we see extra shoppers designing outlier detection into their look at various system prior in the product lifecycle to achieve better outgoing fine in lots of market segments — now not just car, clinical and aerospace,” talked about Greg Prewitt, director of Exensio options at PDF options.

Die place: x, y, and zWith geo-spatial outlier detection strategies, analysis takes area after wafer look at various because the verify results of a die and its neighbors all need to be considered in making the pass/fail resolution. This requires extra computation to be performed, and yield/examine records analytic options help these computations. It can be an IDM’s personal gadget, or a third-party answer that an IDM, foundry, or fabless enterprise would use. depending on the certain technique, the defined local varies. commonly these make intuitive experience. but the definition of “neighbor” can get complex at superior CMOS process nodes, which necessitate a miles subtler definition of “regional.”

despite the business’s efforts to have uniform machine processing across a wafer, the character of semiconductor manufacturing approaches produces geographical patterns that are mirrored in distinct manufacturing metrics. edge dies have lessen yield than a die in the center of a wafer. The spinning of photoresist consequences in radial zones. throughout the litho system there will also be subtle unevenness of the focal point throughout all dies in a multi-die reticle.

With smaller function sizes, these subtle effects occur greater quite simply and display up within the patterns of failing die at wafer test and in subsequent manufacturing steps. Engineers now use these patterns to make choices involving device pass/fail.

Fig. 1: Concentric circles and radial patterns on a wafer. source: Semiconductor Engineering/Anne Meixner

In testing for defective devices, the defects commonly were categorised into random and systematic. The geographical nature of the semiconductor process and multiplied management of defect density have shifted the focal point to systematic defects, with geo-spatial relationships on the wafer and the manufacturing approaches playing a job.

“In typical, these sources of defects essentially under no circumstances appear in a really random manner,” pointed out Dirk de Vries, director analysis and development of silicon lifecycle management at Synopsys. “So system model from the manufacturing exists, and just about everything has a spatial gradient. That’s authentic for parametric residences like layer thicknesses or line widths. They usually have a fairly smooth gradients over the wafer, that means the measured houses of a die can have a undeniable level of predictive price for the properties of its neighbors on the wafer. You might say, ‘yes, but they’ve acquired random defects, and random has no predictive cost.’ It’s not quite so simple as that, as a result of in case you look at wafer manufacturing defects, there exists a mechanism of manufacturing the defects. as an example, it will also be flaking from the wafer part, or within the source of the plasma. The element is there are sources of defects, and they well-nigh under no circumstances seem in a truly random manner.”

The geographical patterns can be viewed in statistics analytic systems, and that they will also be used for yield management to determine frustrating equipment or device mixtures. A collection of engineering stories by means of Intel engineers (1999 to 2005) used wafer test facts, x-y location, and digital chip identification (ECID) to examine the connection between wafer and reliability defect density. Having ECID facilitated information evaluation across multiple examine steps. This enabled them to find distinct patterns in wafer examine outcomes for a die with respect to lot, wafer, x-y location and local vicinity, and its neighbors and the die’s subsequent habits at final examine after the burn-in system. For the native place (a.okay.a. nearby) they seemed on the die within a 5 x 5 location and calculated yield numbers for die marked N, D, T.

Fig. 2: nearby based upon x-y place and N,D, T locations recognized. supply: Semiconductor Engineering/Anne Meixner

in their evaluation, the Intel engineers referred to wafer-to-wafer adaptation changed into twice the size of lot-to-lot model. “Traceability proved to be a powerful device,” they referred to, “for revealing qualities inside wafer patterns of such screw ups. This became especially true for delicate signals buried inside the construction burn-in statistics. Failure evaluation established that these sub-populations have been invariably differentiated by new systematic failure modes or defect distributions.”

followed in 1999, this degree of localization speaks to the complexity of the CMOS method at 0.25 microns. With nowadays’s advanced procedure nodes, these systematic screw ups have extended.

Outlier detection algorithms primarily based upon neighborhoodLocalization gets smaller with these outlier detection strategies based upon geo-spatial relationship of a die in regards to its neighbors. Radial position has an influence on defectivity, and thus yield. For localization of choices of look at various, the concept of neighborhood has predominated. here's adopted by means of taking a look at relationship in the z course.

Localizing dynamic PAT to smaller neighborhoods, like 5 x 5 or 7 x 7, permits engineers to observe the delicate variations from these systematic failure modes. by doing so, engineers can reduce the false negatives/positives.

There had been two tactics to evaluating a die to its neighbors — good die in a nasty local (GDBN), and dangerous die in a great local. over the past two many years, engineers from numerous organizations, including LSI good judgment, Intel, and TI, have posted case reports that justify these apparently draconian selections.

Fig. three: good die in a bad neighborhood based mostly upon x-y area. source: Semiconductor Engineering/Anne Meixner

The GDBN is straight ahead, if a die passes all exams yet a number of its neighbors had been marked unhealthy then the first rate die is now suspect. They may also be assigned outlier after which either failed at wafer sort or marked for extra trying out that the other first rate die might now not receive.

Fig. four: decent die in a nasty local. supply: national devices

unhealthy die in a superb regional is a perplexing time period. Technically, it is not a nasty die if it handed, however its parametrically different.

“greater consumers are trying to get a higher-stage excellent, in order that they’re taking a look at outliers with admire to a die’s nearby. should you analyze all the die around it, they’re expected to parametrically equivalent,” referred to Carl Moore, yield administration professional at yieldHUB. “but sometimes a die’s parametric size may be off via a pair sigma, probably still in the common distribution. ‘whatever thing’s just isn't right about this, because it’s displaying a different parametric price to everything around it.'”

moreover searching in the x and y path for a regional, product engineers can look at selected die region throughout all wafers. “There are also strategies comparable to ZPAT, the place you can analyze within the z axis on a gaggle of wafers. this is very beneficial in discovering defects in masks the place a single die may also always fail or be an outlier,” talked about Moore.

Fig. 5: distinctive wafer maps stacked and failures in Z-course. source: Galaxy Semiconductor

The faulty mask influence on yield seems obtrusive. The parametric outlier application is localized in accordance with a demo dimension of 25 die (customarily 25 wafers per lot). observe that a 5 x 5 regional in the x-y course also has 25 die to look for an outlier. in reality, you’re stacking the wafers and searching for patterns within the z path.

“We had Z-PAT within the marketplace as early as 2005,” observed Wes Smith, CEO of Galaxy Semiconductor. “It became developed for a european tier-1 automotive supplier. This enterprise became drawn to exploring outlier ideas past traditional (even then) DPAT, and that they had been looking at a considerable number of geo-spatial relationships, among them Z-PAT.”

Defining an electrical neighborThe geo-spatial options discussed have strictly regarded actual relationships. Yet even two a long time ago engineering groups pioneering these options recognized the systematic nature of CMOS semiconductor manufacturing influences the definition of nearby. instead of doing a physical neighborhood, they advised selecting a local in line with electrical test records.

“a hard and fast neighborhood choice such as the eight die closets to the position x, y works well in apply when the information pattern is easily varying,” wrote an engineering team from Portland State tuition and LSI good judgment in a 2001 overseas check conference paper. “easy contours had been observed again and again. youngsters, stepper patterns have also been followed and they are no longer easy but systematic. They impose a checkerboard effect throughout the wafer,”

Fig. 6: Stepping pattern checkerboard effect. supply: Semiconductor Engineering/Anne Meixner

After recognizing this demo in IDDQ exams, the group recommended using an information pushed approach to defining the neighborhood and the bounds to be applied, which they known as place averaging. They illustrated its effectiveness with IDDQ measurements. Their technique additionally included the use of residuals of measurements. Nearest neighbor residual (NNR) combines geo-spatial relationships with an arithmetic change of the check parameter. NNR virtually defines a neighborhood primarily based upon similar cost distributions, and this distribution isn't the raw test measurements.

an additional data supply of a die’s parametric performance is on-die measurements, and these too can also be used to define an electrical neighborhood within a die. That permits refinement of the nearby.

“For the geo-spatial innovations to be helpful, there is robust assumption on the technique version in each the x-y and z directions,” talked about Alex Burlak, vice president of test and analytics at proteanTecs. “In superior method nodes, system variation within the chip might be tremendous and stronger additional throughout ICs (regional) or wafers (z course), making the geo spatial recommendations much less useful. therefore, a extra beneficial method is to create an expected bottom line per chip (i.e. taking a ‘personalized medication’ approach), using desktop getting to know and superior analytics utilized to parametric information generated by using on-die widespread chip telemetry (UCT) displays. that you may look at it as PAT per chip in place of lot, wafer, nearby.”

ConclusionAdoption of look at various monitors primarily based upon wafer position with the aid of the wider product engineering group has tremendously elevated within the remaining decade. the provision of third-birthday celebration yield/look at various management programs enables fabless and small IDM’s to use such recommendations.

“The semiconductor business all the time emphasizes the significance for great and reliability of contraptions,” noted Prasad Bachiraju, director for income and consumer solutions at Onto Innovation. “Analytics systems with supply chain integration infrastructure have enabled fabs to perform suggestions and statistical die binning in response to remaining look at various information. using the wafer context and regional of the die with respect to the source wafer has helped to observe test escapes and increase universal reliability of the chips.”

Geo-spatial primarily based outlier detection recommendations allow engineers to localize the video game of “one of those issues isn't just like the others.”

“you have got one set of efficiency targets that you just desire all die to satisfy, as an example 100 micro amps of leakage. however as a result of spatial variation, they don’t all the time hit the mark,” talked about Advantest’s Butler. “So, in test you ask the question ‘When are they distinct and by way of how a lot are they diverse from neighborhood die?’ All these suggestions we're speaking about are premised on wafer position context. That’s why they work so well.”

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